1. Field of Use
This invention pertains to data processing systems and more particularly to interrupt apparatus utilized in conjunction with such systems.
2. Prior Art
As well known, many systems have processing units which employ interrupt apparatus for servicing interrupts from competing devices on a priority basis. Normally, this is achieved by assigning priority interrupt levels to the competeing devices which are compared for enabling the device having the higher priority interrupt gain access to the system or processing unit. After the device's request has been seviced, the processing unit sends out a signal to the devices for indicating its readiness to service new interrupts at the current interrupt level. An example of this type of system is disclosed in U.S. Pat. No. 3,984,820.
While it is possible to initiate level changes in response to program instructions without difficulty, problems arise when making changes while servicing asynchronously arriving external interrupts generated by devices connected to an asynchronous system bus such as that described in U.S. Pat. Nos. 3,993,981 and 4,371,928, assigned to the same assignee as named herein. One way of ensuring reliable switching is to include circuits for detecting when system bus activity has ceased and enabling the level change to take place at that time.
The above appraoch requires a considerable amount of cicuitry and is limited to a system which included a single processing unit. That is, in systems which include more than one processing unit, it is possible for more than one processing unit to change interrupt levels at the same time giving rise to improper notification of such switching to the other devices connected to the system bus. For example, the notification signals simultaneously generated by two processing units could cancel or interfere with one another depending on the relative positioning of each processing unit on the system bus so as to be misinterpreted by the receiving devices.
Accordingly, it is a primary object of the present invention to provide an interrupt change apparatus for use in a multiprocessing system.
It is a further object of the present invention to provide interrupt level change apparatus which operates reliably in a multiprocessing system independent of the number of processing units included in the system.